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precision analog microcontroller, analog i/o with mdio interface, arm cortex - m3 data sheet ADUCM322 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. all rights reserved. technical support www.analog.com features analog input/output multichannel, 1 2 - bit, 1 msps analog - to - digital converter ( adc ) up to 16 adc input channels 0 v to vref analog input range s ingle - ended modes avdd and iovdd monitor s 12- bit voltage output digital - to - analog converters (vdacs) 8 vdacs with a range of 0 v to 2.5 v or av dd outputs voltage compa rator microcontroller arm cortex - m3 processor, 32 - bit risc architecture serial wire port supports code download and debug clocking options 80 mhz phase - locked loop ( pll ) with programmable divider trimmed on - chip oscillator ( 3 %) external 16 mhz crystal option external clock source up to 80 mhz memory 2 128 kb independent f lash/ee memor i es 10,000 cycle f lash/ee endurance 20 - year f lash/ee retention 32 kb sram software triggered in - circuit reprogrammability via management data input/output (mdio) on - chip peripherals mdio slave up to 4 mhz 2 i 2 c, 2 spi, uart multiple general - purpose input/output ( gpio ) ball s : 3.6 v compliant 7 1.2 v compatible when used for mdio 32 - element programmable logic array (pla ) 3 general - purpose timers wake - up timer watchdog timer 16 - bit pulse width modulator ( pwm ) power supply range: 2.9 v to 3.6 v flexible operating modes for low power applications packages and temperature range 6 mm 6 mm , 96- ball csp_ bga package fully specified for ? 40 c to + 105 c ambient operation tools quickstart development system full third - p arty support applications optical networking functional block dia gram figure 1. memory 2 128kb flash 32kb sram arm cortex-m3 processor mux reset ain0 ain5 ain6 ain15 buf_vref2v5 vdac7 ADUCM322 agndx iovddx iogndx genera l purpose i/o ports swdio swclk gpio ports uart 2 spi 2 i 2 c ext irqs mdio pla internal channels: temperature, av dd , iov dd 2.5v band gap dm a nvic reset system serial wire clock system 32.768khz 16mhz osc 80mhz pll 3 gp timer wd timer w ake-u p timer pwm vdac sar adc comparator xtalo xtali eclkin avddx dgndx pwm0 t o pwm6 1.8 v ldo vdac0 vdac 13754-001
ADUCM322* product page quick links last content update: 08/30/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ADUCM322 evaluation board? documentation application notes ? an-1310: flash programming via mdio?protocol type 8 ? an-1322: aducm320 code execution speed data sheet ? ADUCM322: precision analog microcontroller, analog i/o with mdio interface, arm cortex-m3 data sheet ? ADUCM322i: precision analog microcontroller, analog i/ o with mdio interface, arm cortex-m3 data sheet user guides ? ug-868: aducm320i/ADUCM322/ADUCM322i reference manual ? ug-910: ADUCM322 development systems getting started tutorial tools and simulations ? ADUCM322 cmsis pack design resources ? ADUCM322 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ADUCM322 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ADUCM322 data sheet rev. 0 | page 2 of 23 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 1 general description ......................................................................... 3 specifications ..................................................................................... 4 microcontroller electrical specifications .................................. 4 absolute maximum ratings ..................................................... 14 esd caution ................................................................................ 14 ball configuration and function descriptions .......................... 15 typical performance characteristics ........................................... 20 recommended circuit and component values ........................ 21 packaging and ordering information ......................................... 23 outline dimensions ................................................................... 23 ordering guide .......................................................................... 23 revision history 2 / 1 6 revision 0 : initial version
data sheet ADUCM322 rev. 0 | page 3 of 23 general description the ADUCM322 is a fully integrated , single package device that incorporate s high performance analog peripherals together with digital peripherals controlled by an 80 mhz arm ? cortex? - m3 processor an d integral flash for code and data. the adc on the ADUCM322 provides 1 2 - bit , 1 msps data acquisition on up to 16 input ball s. a dditionally , chip temperature and supply vol tages can be measured. the adc input voltage range is 0 v to vref. a sequencer is provided , whi ch allows a user to select a set of adc channels to measure in sequence without software in volvement during the sequence. the sequence can optionally repeat automatically at a user selectable rate. up to eight v dacs are provided with output ranges that are programmable to one of two voltage ranges. the ADUCM322 can be configured so that the digital and analog outputs retain their output voltages through a watchdog or software reset sequence. thus , a product can remain functional even while the ADUCM322 is resetting itself. the ADUCM322 ha s a low power arm cortex - m3 proce ssor and a 32 - bit risc machine that offers up to 100 mips peak perfor - mance. also integrated on - chip are 2 128 kb f lash/ee memory blocks and 32 kb of sram. the flash comprises two separate 128 kb blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block. the ADUCM322 ope rate s from an on - chip oscillator or a 16 mhz external crystal and a pll at 80 mhz. this clock can optionally be divided down to reduce current consumption. additional low power modes can be set via software. in normal operating mode , the ADUCM322 digital core consumes about 300 a per mhz. the device includes an mdio interface capable of operating at up to 4 mhz. the capability to simultaneously execute from one flash block and write/erase the other flash block makes the ADUCM322 ideal for 10g, 40g , and 100g optical applications. in addition , the nonerasable kernel code plus flags in user flash provide assistance by allow ing user code to robustly switch between the two blocks of user flash code and data spaces . the ADUCM322 integrate s a range of on - chip peripherals that can be configured under software control , as required in the application. these peripherals include 1 ua rt, 2 i 2 c , and 2 spi s erial input/output communication controllers, gpio, 32- element pla , three general - purpose timers , plus a wake - up timer and system watchdog timer. a 16- bit pwm with seven output channels is also provided. gpio ball s on the device power up in high impedance input mode . in output mode , the software choose s between open - drain mode and push - pull mode. the pull - up resistor s can be disabled and enabled in software. in gpio output mode , the inputs can remain enabled to monitor the ball s. the gpio ball s can also be programmed to h andle digital or analog peripheral signals ; in su ch case s, the ball characteristics are matched to the specific requirement. a large support ecosystem is available for the a rm cortex - m3 processor to ease product development of the ADUCM322 . acces s is via the arm serial wire debug port (sw - dp ). on - chip factory firmware supports in - cir cuit serial download via mdio . these features are incorporated into a quickstart ? development system , supporting this precision a nalog microcontroller family.
ADUCM322 data sheet rev. 0 | page 4 of 23 specifications microcontroller elec trical s pecifications avdd = iovdd = vdd1 = 2.9 v to 3.6 v ( s ee figure 12 ) , m ax imum difference between supplies = 0.3 v, vref = 2.5 v internal reference, f core = 80 mhz, t a = ?40c to + 10 5c, unless otherwise noted . the p ower - up sequence must be vdd1, iovdd x , and av dd x , but no dela ys in the sequence are required . table 1 . parameter symbol min typ max unit test conditions/comments adc basic specifications single - ended mode , unless otherwise stated adc power - up time 5 s data rate f sample 1 msps dc accuracy 1 1 2 bits 1 lsb = 2.5 v/2 1 2 resolution 1 16 bits number of data bits integral nonlinearity inl 1 .75 lsb 2.5 v internal reference ; 1 lsb = 2.5 v/2 1 2 1.75 lsb 2.5 v external reference ; 1 lsb = 2.5 v/2 1 2 differential nonlinearity dnl ? 0.99 0. 75 +1 .5 lsb 2.5 v internal reference ; 1 lsb = 2.5 v/2 1 2 0.75 lsb 2.5 v external reference ; 1 lsb = 2.5 v/2 1 2 dc code distribution 3 lsb adc input 1.25 v ; 1 lsb = 2.5 v/ 2 1 2 adc endpoint errors offset error 200 v drift 1 ? 3.92 0.3 + 1.2 1 v/c using 2.5 v external reference match 1 lsb matching compared to ain8 full - scale error 400 v gain drift 1 ? 4 + 5 v /c full - scale error drift minus offset error drift match lsb adc dynamic performance f in 2 h sine wae, f sample sps inut filter , c l 2 nf signal - to - noise ratio snr b inclues istortion an noise coonents total haronic distortion thd b pea haronic or surious noise b channel - to - channel crosstal b measure on aacent channels adc input inut oltage ranges single - ene moe agnd ref coliance agnd add l eaage current na inut current a/ at msps a/ sps a/ sps , adccnc , bits 2 xe inut caacitance 2 f during adc acuisition on - chip oltage reference 2 f fro ref2 to agnd reference i s easure with all adc an dacs enale accurac t a 2c reference teerature coefficient /c power sul reection ratio psrr b internal ref power - on tie s
data sheet ADUCM322 rev. 0 | page 5 of 23 parameter symbol min typ max unit test conditions/comments external reference input range 1 1.8 2.5 v adc input c urrent 200 a buffered reffernce output output voltage 2.504 v accuracy 8 mv t a = 25c, load = 1.2 ma reference temperature coefficient 1 15 v/c 100 nf from buf_vref2v5 to agnd4 output impedance 10 ? t a = 25c load current 1 1.2 ma vdac channel specifications r l = 5 k?, c l = 100 pf 2 dc accuracy 1 12 bits 1 lsb = 2.5 v/2 12 resolution 1 12 bits number of data bits relative accuracy 3 inl 4 lsb 1 lsb = 2.5 v/2 12 differential nonlinearity 3 dnl ?0.99 +1 lsb guaranteed monotonic, 1 lsb = 2.5 v/2 12 offset error 3 15 mv 2.5 v internal reference, dac output code 0 drift 1 8 v/c gain error 4 0.3 0.85 % 0 v to internal v ref range 0.4 1 % 0 v to avdd range drift 6.5 ppm/c excluding reference drift mismatch 0.1 % % of full scale on dac0 analog outputs output voltage range 1 1 0.15 2.5 v output voltage range 2 1 0.15 avddx ? 0.15 v output impedance 2 ? dac ac characteristics output settling time 10 s settled to 1 lsb glitch energy 20 nv - sec 1 lsb change when the maximum number of bits changes simultane - ously in the dacxdat register comparator input offset voltage 10 mv bias current 1 na voltage range 1 agndx avddx ? 1.2 v capacitance 7 pf hysteresis 1 8.5 15 mv when enabled in software response time 7 s afecomp , bits [2:1] = 0 temperature sensor indicates die temperature, see figure 9 resolution 0.5 c when precision calibrated by the user 5 accuracy 1 1.34 1.43 v adc measured voltage for temperature sensor channel without calibrati on, t a = 25 c power - on reset por 2.85 2.9 v watchdog timer wdt timeout period 32 sec default at power - up flash/ee memory endurance 1 10,000 cycles data retention 1 20 years t j = 85c
ADUCM322 data sheet rev. 0 | page 6 of 23 parameter symbol min typ max unit test conditions/comments digital inputs input leakage current logic 1 gpio 1 na v ih = v dd , pull - up resistor disabled logic 0 gpio 10 na v il = 0 v, pull - up resistor disabled prtaddrx input leakage current 16 a v in = 0 v to 1.8 v, due to weak pull - up resistors to 1.8 v input voltage 0.84 1.5 v external resistor 91 k? 1% to ground ; r ange for cfp msa high 1 input capacitance, all ball s except mck , mdio , prtaddr x, and xtal x 10 pf input capacitance mck, prtaddrx 6.5 pf mdio 8.5 pf ball capacitance xtali 5 pf xtalo 5 pf logic inputs gpio input voltage low v inl 0.25 iovddx v high v inh 0.58 iovddx v mdio prtaddrx input voltage low v inl 0.36 v high v inh 0.84 v mck, mdio input voltage setup time 10 ns; h old time 10 ns; mck/mdio low v inl 0.36 v high v inh 0.84 v xtali input voltage low v inl 1.1 v high v inh 1.7 v pull - up current 30 120 a v in = 0 v, see figure 10 pull - down c urrent 30 100 a v in = 3.3 v, see figure 10 logic outputs all digital outputs excluding xtalo gpio output voltage 6 high v oh iovddx ? 0.4 v i source = 2 m a low v ol 0.4 v i sink = 2 ma gpio short - circuit current 1 11 ma see figure 11 mdio output voltage high v oh 1.0 v i source = 4 m a low v ol 0.2 v i sink = 4 m a delay time 100 ns mck to mdio out oscillators internal system oscillator 16 mhz accuracy 0.5 3 % system pll 80 mhz main system clock external crystal oscillator 16 mhz can be selected in place of the internal oscillator 32 khz internal oscillator 32.768 khz use for watchdog accuracy 5 20 % external clock 0.05 80 mhz can be selected in place of pll start - up time processor clock = 80 mhz at power - on 40 ms por to first user code execution after other reset 1.5 ms reset to first user code execution from all power - down modes 1.25 s
data sheet ADUCM322 rev. 0 | page 7 of 23 parameter symbol min typ max unit test conditions/comments programmable logic array pla propagation delay ball 17 ns from input ball to output ball element 1.5 ns per pla cell external interrupts pulse width 1 level triggered 7 ns edge triggered 1 ns power requirements 7 power supply voltage range avddx to agndx and iovddx to dgndx 1 2.9 3.3 3.6 v analog power supply currents avddx current 4.9 ma analog peripherals in idle mode digital power supply current iovddx current in normal mode 2.7 ma all gpio pull - up resistors enabled vddx current normal mode 29 ma clock divide r ( cd ) = 0 (80 mhz clock) , executing typical code 20 ma cd = 1 , executing typical code 10 ma cd = 7 , executing typical code core_sleep mode 16 ma sys_sleep mode 8 ma hibernate mode 4 ma additional power supply currents adc 4.1 ma continuously converting at 100 ksps dac 340 a per powered up dac, excluding load current total s upply c urrent 37 ma vdd1, iovddx, avddx connected together ; c ondition when entering user code: p eripheral clocks on, peripherals idle, no load currents thermal performance impedance junction to ambient 45 c/w jedec 2s2p 1 these specifications are not production tested but are guaranteed by design and/or characterization data at production release. 2 the data in this section also applies for a load of r l =1 k? and c l = 100 pf but only an output range of 0 v to 2.5 v.however, this specification is not production tested. 3 dac l inearity is calculated using a reduced code range of 100 to 3900. 4 dac gain error is calculated using a reduced code range of 100 to an internal 2.5 v v ref . 5 due to self heating , intern al temperature measurements can not b e used to predict external temperatures. this value is only relevant after user calibration and only for internal and external conditions identical to those at calibration. 6 the average current from all gpio ball s must not exceed 3 ma per ball . 7 power fi gures exclude any load currents to external circuits.
ADUCM322 data sheet rev. 0 | page 8 of 23 timing specifications i 2 c timing table 2. i 2 c timing in standa rd mode (100 khz) slave parameter description min typ max unit t l scl low pulse width 4.7 s t h scl high pulse width 4.0 ns t shd start condition hold time 4.0 s t dsu data setup time 250 ns t dhd data hold time (sda held internally for 300 ns after falling edge of scl) 0 3.45 s t rsu setup time for repeated start 4.7 s t psu stop condition setup time 4.0 s t buf bus-free time between a stop conditio n and a start condition 4.7 s t r rise time for both slc and sda 1 s t f fall time for both slc and sda 15 300 ns t vd;dat data valid time 3.45 s t vd;ack data valid acknowledge time 3.45 s table 3. i 2 c timing in fast mode (400 khz) slave parameter description min typ max unit t l scl low pulse width 1.3 s t h scl high pulse width 0.6 ns t shd start condition hold time 0.3 s t dsu data setup time 100 ns t dhd data hold time (sda held internally for 300 ns after falling edge of scl) 0 s t rsu setup time for repeated start 0.6 s t psu stop condition setup time 0.3 s t buf bus-free time between a stop conditio n and a start condition 1.3 s t r rise time for both scl and sda 20 300 ns t f fall time for both scl and sda 15 300 ns t vd;dat data valid time 0.9 s t vd;ack data valid acknowledge time 0.9 s figure 2. i 2 c compatible interface timing sda (i/o) msb lsb ack msb 1 9 8 2?7 1 scl (i) ps start condition repeated start stop condition s(r) t dsu t h t l t shd t psu t dsu t buf t dhd t vd; dat t vd; ack t r t f t f t r t dhd t rsu 13754-010
data sheet ADUCM322 rev. 0 | page 9 of 23 spi timing table 4. spi master mode timing (phase mode = 1) parameter description min typ max unit t sl sclk low pulse width (spidiv + 1) t hclk /2 ns t sh sclk high pulse width (spidiv + 1) t hclk /2 ns t dav data output valid after sclk edge 0 3 ns t dsu data input setup time before sclk edge ? sclk ns t dhd data input hold time after sclk edge sclk ns t df data output fall time sclk ns t dr data output rise time 25 ns t sr sclk rise time 25 ns t sf sclk fall time 20 ns figure 3. spi master mode timing (phase mode = 1) sclk (polarity = 0) sclk (polarity = 1) mosi msb bits 6 to 1 lsb miso msb in bits 6 to 1 lsb in t sh t sl t sr t sf t dr t df t dav t dsu t dhd 13754-011
ADUCM322 data sheet rev. 0 | page 10 of 23 table 5. spi master mode timing (phase mode = 0) parameter description min typ max unit t sl sclk low pulse width (spidiv + 1) t hclk /2 ns t sh sclk high pulse width (spidiv + 1) t hclk /2 ns t dav data output valid after sclk edge 0 3 ns t dosu data output setup before sclk edge ? sclk ns t dsu data input setup time before sclk edge sclk ns t dhd data input hold time after sclk edge sclk ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk rise time 20 ns t sf sclk fall time 20 ns figure 4. spi master mode timing (phase mode = 0) sclk (polarity = 0) sclk (polarity = 1) t sh t sl t sr t sf mosi msb bits 6 to 1 lsb miso msb in bits 6 to 1 lsb in t dr t df t dav t dosu t dsu t dhd 13754-012
data sheet ADUCM322 rev. 0 | page 11 of 23 table 6. spi slave mode timing (phase mode = 1) parameter description min typ max unit t cs e cs e to sclk edge 10 ns t cs e m cs high time between active periods sclkx ns t sl sclk low pulse width (spidiv + 1) t hclk ns t sh sclk high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclk edge 20 ns t dsu data input setup time before sclk edge 10 ns t dhd data input hold time after sclk edge 10 ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk rise time 1 ns t sf sclk fall time 1 ns t sfs cs e high after sclk edge 20 ns figure 5. spi slave mode timing (phase mode = 1) sclk (polarity = 0) sclk (polarity = 1) t sh t sl t sr t sf t sfs miso msb bits 6 to 1 lsb mosi msb in bits 6 to 1 lsb in t dhd t dsu t dav t dr t df cs t cs t csm 13754-013
ADUCM322 data sheet rev. 0 | page 12 of 23 table 7. spi slave mode timing (phase mode = 0) parameter description min typ max unit t cs e cs e to sclk edge 10 ns t cs e m cs high time between active periods sclkx ns t sl sclk low pulse width (spidiv + 1) t hclk ns t sh sclk high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclk edge 20 ns t dsu data input setup time before sclk edge 10 ns t dhd data input hold time after sclk edge 10 ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk rise time 1 ns t sf sclk fall time 1 ns t docs data output valid after cs e edge 20 ns t sfs cs e high after sclk edge 10 ns figure 6. spi slave mode timing (phase mode = 0) sclk ( polarity = 0) cs sclk ( polarity = 1) t sh t sl t sr t sf t sfs miso mosi msb in bits 6 to 1 lsb in t dhd t dsu msb bits 6 to 1 lsb t docs t dav t dr t df t cs t csm 13754-014
data sheet ADUCM322 rev. 0 | page 13 of 23 table 8. mdio vs. mdc timing parameter description min typ max unit t setup mdio setup before mck edge 10 ns t hold mdio valid after mck edge 10 ns t delay data output after mck edge 100 ns figure 7. mdio timing mdk vih vil vih vil voh vol cfp input mdio cfp input mdio cfp o utput t setup t hold t delay 13754-015
ADUCM322 data sheet rev. 0 | page 14 of 23 absolute maximum rat ings table 9 . parameter rating any b all to gnd ? 0.3 v to + 3.9 v any res1 type ball to gnd ? 0.3 v to +2.8 v mdio , 1 mck and prtaddr0 to prtaddr 4 in mdio mode to gnd ?0.3 v to +2.1 v between a ny of avddx, iovdd x , and vdd1 ball s ? 0.3 v to + 0.3 v any i type ball to gnd 2 ? 0.3 v to iovdd x + 0.3 v any res type , ai type , or ao type ball to gnd 3 ? 0.3 v to avdd x + 0.3 v adc _ refp to gnd ? 0.3 v to avdd x + 0.3 v total p ositive gpio ball currents 0 ma to 30 ma total n egative gpio ball currents ? 30 ma to 0 ma maximum power dissipation 1 w operating ambient temperature range ? 40c to + 10 5c storage t emperature range ? 65c to + 160c operating junction temperature range ? 40c to + 120c electrostatic discharge (esd) human body model (hbm) 2 kv field induced charged device mode (ficdm) 1 kv 1 note this ball is always in mdio mode . 2 this limit does not apply if no current can be drawn by external circuits on iovddx , because then iovdd follow s to a suitable level. 3 this limit does not apply if no current can be drawn by external circuits on avddx , because then avdd follow s to a suitable level. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specif ication is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. all requirements applicable to each ball must be met. where multiple limits apply to a ball , eac h one must be met individually. t he limits apply according to the functionality of the ball s at the time. balls that can be either analog or digital, that is, that have two types indicated in the ball descriptions, must meet the limits for both types. for ball types, see table 10. when powered up, it is required that all ground balls and adc_refn be connected together to a node referred to as gnd in table 9 . the limits that are listed must be reduced by any difference between any gnds. also, it is required that avdd3 is connected to avdd4 an d that iovdd1 to iovdd3 are connected together. esd caution
data sheet ADUCM322 rev. 0 | page 15 of 23 pin configuration and fu nction descriptions figure 8. pin configuration table 10. pin function description s pin no. mnemonic type 1 description a1 reserved res no connect. leave this ball unconnected. a2 reserved res connect to agnd . a3 reserved res1 connect to avdd_reg1. a4 reserved res1 connect to avdd_reg1. a5 reserved res connect to agnd . a6 dgnd s power supply ground . a7 reserved res connect to agnd . a8 reserved res1 connect to avdd_reg1. a9 reserved res1 connect to avdd_reg1. a10 reserved res connect to agnd . a11 iref ai reference current. this ball generates the reference current and is set by an external resistor, r ext . connect a 3.3 k? r ext from iref to d gnd. b1 iovdd1 s 3.3 v gpio supply. b2 reset i reset input (active low). an internal pull - up resistor is included. b3 p3.3/prtaddr3/plai[15] i/o digital input/output port 3.3 (p3.3). mdio port address bit 3 (prtaddr3). see the d igital i nputs parameter in table 1 for details. output of pla element 15 (plai[15]). b4 reserved res no connect. leave this ball unconnected. b5 reserved res no connect. leave this ball unconnected. b6 dgnd s power supply ground . 1 a b c d e f g h j k l 2 3 4 5 6 7 8 9 10 1 1 rese r ved rese r ved rese r ved iovdd1 iognd1 p3.3/ pr t addr3/ plai[15] p0.0/ sclk0/ plai[0] rese r ved rese r ved rese r ved rese r ved rese r ved iref rese r ved dgnd dgnd2 swclk ain15/ p4.7 ain14/ p4.6 ain12/ p4.4 ain 1 1/ buf_ vref2v5 ain10 ain7 ain2 ain1 ain0 agnd1 vdac4 vdac7/ p5.2 vdac6/ p5.1 xt ali iovdd3 iognd3 vdac3/ p5.0 vdac1 vdd1 a vdd3 agnd2 agnd3 ain3 ain4 ain6 ain5 ain9/ p4.3 ain8/ p4.2 vdac0/ p5.3 vdac2/ p3.7/ plao[29] vdac5 dgnd1 agnd4 ain13/ p4.5 a vdd4 swdio iognd2 iovdd2 dgnd rese r ved rese r ved rese r ved rese r ved reset p1.0/sin/ eclkin/ plai[4] p1.2/ pwm0/ plai[6] p1.1/sout/ placlk1/ plai[5] p2.4/irq5/ adcconv/ pwm6/ plao[18] p1.3/ pwm1/ plai[7] p1.4/ pwm2/ sclk1/ plao[10] p1.5/ pwm3/ miso1/ plao[ 1 1] p1.6/ pwm4/ mosi1/ plao[12] p1.7/irq1/ pwm5/ cs1/ plao[13] p2.0/irq2/ pwmtrip/ placlk2/ plai[8] p2.2/ irq4/por/ clkout/ plai[10] p2.3/bm p0.2/ mosi0/ plai[2] p0.5/ sda0/ plao[3] p2.6/ irq7/ plao[20] p0.7/ sda1/ plao[5] p0.6/ scl1/ plao[4] p3.0/ pr t addr0/ plai[12] p3.1/ pr t addr1/ plai[13] p2.7/ irq8/ plao[21] p3.5/ mck/ plao[27] xt alo mdio p0.4/ scl0/ plao[2] p0.3/ irq0/cs0/ placlk0/ plai[3] p0.1/ miso0/ plai[1] p3.2/ pr t addr2/ plai[14] p3.4/ pr t addr4/ plao[26] a vdd_ reg0 a vdd_ reg1 vref_1v2 adc_ ref p adc_ refn dvdd_ 2v5 dvdd_1v8 ADUCM322 top view (not to scale) 13754-002 digital pins analog pins
ADUCM322 data sheet rev. 0 | page 16 of 23 pin no. mnemonic type 1 description b7 reserved res no connect. leave this ball unconnected. b8 reserved res no connect. leave this ball unconnected. b9 p1.0/sin/eclkin/plai[4] i/o digital input/output port 1.0 (p1.0). uart input (sin). external input clock (eclkin). input to pla element 4 (plai[4]). b10 p1.1/sout/placlk1/plai[5] i/o digital input/output port 1.1 (p1.1). uart output (sout) . pla clock 1(placlk1). input to pla element 5 (plai[5]). b11 p1.2/pwm0/plai[6] i/o digital input/output port 1.2 (p1.2). pwm output 0 (pwm0). input to pla element 6 (plai[6]). c1 iognd1 s ground for iovdd1. c2 p0.0/sclk0/plai[0] i/o digital i nput /o utput port 0.0 (p0.0). spi0 clock (sclk0). input to pla element 0 (plai[0]). c3 p2.3/bm i/o digital input/output port 2.3 (p2.3). boot mo de (bm). this ball determines the start - up sequence after every reset. pull - up is enabled at power - up. c4 p2.2/irq4/ por /clkout/plai[10] i/o digital input/output port 2.2 (p2.2). external interrupt 4 (irq4). reset output ( por ). this ball function is an output and it is the default for ball c4. clock output (clkout). input to pla element 10 (plai[10]). c5 p2.0/irq2/pwmtrip/placlk2/plai[8] i/o digital input/output port 2.0 (p2.0). external interrupt 2 (irq2). pwm trip (pwmtrip). pla input clock 2 (placlk2). input to pla element 8 (plai[8]). c6 p1.3/pwm1/plai[7] i/o digital input/output port 1.3 (p1.3). pwm output 1 (pwm1). input to pla element 7 (plai[7]). c7 p1.4/pwm2/sclk1/plao[10] i/o digital input/output port 1.4 (p1.4). pwm output 2 (pwm2). spi1 clock (sclk1). output of pla element 10 (plao[10]). c8 p1.5/pwm3/miso1/plao[11] i/o digital input/output port 1.5 (p1.5). pwm output 3 (pwm3). spi1 master in, slave out (miso1). output of pla element 11 (plao[11]). c9 p1.6/pwm4/mosi1/plao[12] i/o digital input/output port 1.6 (p1.6). pwm output 4 (pwm4). spi1 master out, slave input (mosi1). output of pla element 12 (plao[12]). c10 p1.7/irq1/pwm5/cs1/plao[13] i/o digital input/output port 1.7 (p1.7). external interrupt 1 (irq1). pwm output 5 (pwm5). spi1 chip select 1 (cs1). when using spi1, configure this ball as cs1. output of pla element 13 (plao[13]).
data sheet ADUCM322 rev. 0 | page 17 of 23 pin no. mnemonic type 1 description c11 p3.4/prtaddr4/plao[26] i/o digital input/output port 3.4 (p3.4). mdio port address bit 4 (prtaddr4). see the d igital i nputs parameter in table 1 for details. output of pla element 26 (plao[26]). d1 p0.2/mosi0/plai[2] i/o digital input/output port 0.2 (p0.2). spi0 master out, slave in (mosi0). input to pla element 2 (plai[2]). d2 p0.1/miso0/plai[1] i/o digital input/output port 0.1 (p0.1). spi0 master in, slave out (miso0). input to pla element 1 (plai[1]). d3 p3.2/prtaddr2/plai[14] i/o digital input/output port 3.2 (p3.2). mdio port address bit 2 (prtaddr2). see the d igital i nputs parameter in table 1 for details. input to pla element 14 (plai[14]). d9 p2.4/irq5/adcconv/pwm6/plao[18] i/o digital input/output port 2.4 (p2.4). external interrupt 5 (irq5). external input to start adc conversions (adcconv). pwm output 6 (pwm6). output of pla element 18 (plao[18]). d10 dgnd2 s digital ground 2. connect to dgnd1. d11 iovdd2 s 3.3 v gpio supply . e1 p0.5/sda0/plao[3] i/o digital input/output port 0.5 (p0.5). i 2 c0 serial data (sda0). output of pla element 3 (plao[3]). e2 p0.4/scl0/plao[2] i/o digital input/output port 0.4 (p0.4). i 2 c0 serial clock (scl0). output of pla element 2 (plao[2]). e3 p0.3/irq0/cs0/placlk0/plai[3] i/o digital input/output port 0.3 (p0.3). external interrupt 0 (irq0). spi0 chip select 0 (cs0). when using spi0, configure this ball as cs0. pla clock 0 (placlk0). input to pla element 3 (plai[3]). e9 swclk i serial wire debug clock. e10 swdio i/o serial wire bidirectional data. e11 iognd2 s ground for iovdd2. f1 p2.6/irq7/plao[20] i/o digital input/output port 2.6 (p2.6). external interrupt 7 (irq7). output of pla element 20 (plao[20]). f2 p0.7/sda1/plao[5] i/o digital input/output port 0.7 (p0.7). i 2 c1 serial data (sda1). output of pla element 5 (plao[5]). f3 p0.6/scl1/plao[4] i/o digital input/output port 0.6 (p0.6). i 2 c1 serial clock (scl1). output of pla element 4 (plao[4]). f9 avdd_reg0 ao analog regulator 0 supply. a 470 nf capacitor to agnd4 must be connected to this ball to stabilize the internal 2.5 v regulator that supplies the adc. f10 avdd_reg1 ao analog regulator 1 supply. output of 2.5 v on - chip ldo regulator. a 470 nf capacitor to agnd4 must be connected to this ball. f11 vref_1v2 s 1.2 v reference. this ball cannot be used to source current externally. connect vref_1v2 to agndx via a 470 nf capacitor. g1 p2.7/irq8/plao[21] i/o digital input/output port 2.7 (p2.7). external interrupt 8 (irq8). output of pla element 21 (plao[21]).
ADUCM322 data sheet rev. 0 | page 18 of 23 pin no. mnemonic type 1 description g2 p3.1/prtaddr1/plai[13] i/o digital input/output port 3.1 (p3.1). mdio port address bit 1 (prtaddr1). see the d igital i nputs parameter in table 1 for details. input to pla element 13 (plai[13]). g3 p3.0/prtaddr0/plai[12] i/o digital input/output port 3.0 (p3.0). mdio port address bit 0 (prtaddr0). see the d igital i nputs parameter in table 1 for details. input to pla element 12 (plai[12]). g9 ain15/p4.7 ai/i/o analog input 15 (ain15). digital input/output port 4.7 (p4.7). g10 ain13/p4.5 ai/i/o analog input 13 (ain13). digital input/output port 4.5 (p4.5). g11 avdd4 s adc supply (3.3 v). h1 p3.5/mck/plao[27] i/o digital input/output port 3.5 (p3.5). mdio clock (mck). see the digital inputs parameter in table 1 for more details. output of pla element 27 (plao[27]). h2 xtalo o output from the crystal oscillator inverter. when not using an external crystal, leave xtalo unconnected. h3 mdio i/o mdio data. h9 ain14/p4.6 ai/i/o analog input 14 (ain14). digital input/output port 4.6 (p4.6). h10 ain12/p4.4 ai/i/o analog input 12 (ain12). digital input/output port 4.4 (p4.4). h11 agnd4 s ground for avdd4, avdd_reg0, and avdd_reg1. j1 iovdd3 s 3.3 v gpio supply. j2 xtali i input to the crystal oscillator inverter and input to the internal clock generator circuits. when not using an external crystal, connect xtali to dgnd. j3 vdac7/p5.2 ao/i/o voltage dac7 output (vdac7). digital input/output port 5.2 (p5.2). j4 vdac4 ao voltage dac4 output (vdac4). j5 agnd1 s analog ground for vdd1. j6 ain0 ai analog input 0. j7 ain1 ai analog input 1. j8 ain2 ai analog input 2. j9 ain7 ai analog input 7. j10 ain10 ai analog input 10. j11 ain11/buf_vref2v5 ai/ao analog input 11 (ain11). buffered 2.5 v bias (buf_vref2v5). the maximum load is 1.2 ma. connect buf_vref2v5 to agndx via a 100 nf capacitor. k1 iognd3 s ground for iovdd3 . k2 dvdd_2v5 ao 2.5 v digital supply. a 470 nf capacitor to iognd3 must be connected to this ball to stabilize the internal 2.5 v regulator that supplies the analog digital control. k3 vdac6/p5.1 ao/i/o voltage dac6 output (vdac6). digital input/output port 5.1 (p5.1). k4 vdac3/p5.0 ao/ i/o voltage dac3 output (vdac3). digital input/output port 5.0 (p5.0). k5 vdac1 ao voltage dac1 output. k6 vdd1 s 3.3 v supply for digital die. k7 agnd2 s esd ground for pad ring. k8 ain3 ai analog input 3. k9 ain6 ai analog input 6. ain6 is also the positive input for the comparator. k10 ain9/p4.3 ai/i/o analog input 9 (ain9). digital input/output port 4.3 (p4.3).
data sheet ADUCM322 rev. 0 | page 19 of 23 pin no. mnemonic type 1 description k11 adc_refp ao/a decoupling capacitor connection for adc reference buffer. connect this ball to a 4.7 f capacitor to the adc_refn ball. adc_refp can be overdriven by an external reference. l1 dgnd1 s digital ground 1 for dvdd_1v8. l2 dvdd_1v8 ao 1.8 v digital supply. a 470 nf capacitor to dgnd1 must be connected to this ball to stabilize the internal 1.8 v regulator that supplies flash memory and the arm cortex - m3 processor. l3 vdac5 ao voltage dac5 output (vdac5). l4 vdac2/p3.7/plao[29] ao/i/o voltage dac2 output (vdac2). digital input/output port 3.7 (p3.7). output of pla element 29 (plao[29]). l5 vdac0/p5.3 ao/i/o voltage dac 0 output (vdac0). digital input/output port 5.3 (p5.3) . l6 avdd3 s vdac supply (3.3 v). l7 agnd3 s ground for avdd3. l8 ain4 ai analog input 4. l9 ain5 ai analog input 5. ain5 can be the negative input for the comparator. l10 ain8/p4.2 ai/i/o analog input 8 (ain8). digital input/output port 4.2 (p4.2). l11 adc_refn ao/a decoupling capacitor connection for adc reference buffer . connect this ball to agnd4. 1 res and res1 are reserved, s is s upply , ai is analog input, i is digital input, i/o is input/output, ao is analo g output, and o is digital output .
ADUCM322 data sheet rev. 0 | page 20 of 23 typical performance characteristics figure 9. temperature measurement vs. internal temperature (v dd = 3.3 v, 50 ksps) figure 10. pull-up/pull-down ball current vs. ball voltage (v dd = 3.3 v, t a = 25c) figure 11. output voltage vs. load current figure 12. vdd1 pow er-on requirements 25000 30000 35000 40000 45000 50000 ?60 ?40 ?20 0 20 40 60 80 100 120 adccode(lsb16) temperature (c) device 1 device 2 device 3 device 4 device 5 13754-003 ?10 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ball current (a) ball voltage (v) maximum pull up minimum pull up minimum pull down maximum pull down 13754-004 0 0.5 1.0 1.5 2.0 2.5 3.0 2 6 10 14 16 0481 2 output vol t age (v) load current (ma) v oh maximum v oh minimum v ol minimum v ol maximum 13754-007 time (not to scale) 3.6 40ms min vdd1 (v) vdd1 must be above 3v for at least 40ms to complete por after 40ms vdd1 must stay above 2.9v including noise excursions 3.0 2.9 13754-008
data sheet ADUCM322 rev. 0 | page 21 of 23 applications informa tion recommended c ircuit and c omponent v alues figure 13 shows a typical connection diagram for the ADUCM322 . supp lies and regulators must be adequately decoupled with c apacitors connected between the avddx, dvdd_x, avdd_regx, iovddx, and vdd1 balls and their associated gnd balls (agndx, iogndx, and dgndx ). table 10 indicates which ground balls are paired with which supply balls. there are four digital supply b alls : iovdd1, iovdd2, iovdd3, and vdd1. decouple these balls with a 100 nf capacitor placed as near as possible to each of the four balls and their associated ground balls (iogndx and agnd1, respectively). in addition, place a 10 f capacitor conveniently near to these balls. similarly, the analog supply ball s, avdd3 and avdd4, each requi re a 100 nf capacitor placed as near as possible to each ball and its associated agndx ball, and place a 10 f capacitor conveniently near to these balls. the adc reference requires a 4.7 f capacitor placed between adc_refp and adc_refn and located as nea r as possible to each ball. adc_refn must be connected directly to agnd4. t he ADUCM322 contain s four internal regulators. t h ese regulators require external decoupling capacitors. the dvdd_1v8 and dvdd_2v5 balls each require a 470 nf capacitor to dgnd1 and iognd3, respectively. avdd_reg0 and avdd_reg1 each require a decoupling capacitor to agnd4. the avdd_reg1 output ball must be connected to b all a3, b all a4, b all a8 , and b all a9 . c onnect the iref ball to d gnd via a standard 3. 3 k? resistor. take care in the layout to ensure that currents flowing from the ground end of each decoupling capacitor to its associated ground ball sha re as little track as possible with other ground currents on the printed circuit board.
ADUCM322 data sheet rev. 0 | page 22 of 23 figure 13. recommended circuit and component values reset reset adc_refp g n d d g n d s w d i o t x s w c l k avdd a v d d 3 a v d d 4 v r e f _ 1 v 2 i r e f adc_refn avdd_reg0 avdd_reg1 a g n d 1 a g n d 3 a g n d 2 f9 l11 k11 a11 f11 h11 l7 k7 j5 f10 a g n d 4 3.3k ? 0.47f 4.7f 0.47f 0.47f b2 c1 e11 p1.1/sout/placlk1/plai[5] j2 swdio h2 a3 a9 1 2 p f d g n d d g n d ADUCM322 reserved reserved reserved reserved reserved reserved reserved xtalo xtali reset reset a4 a8 b4 b8 b5 vdd1 reserved b7 swclk p1.0/sin/eclkin/plai[4] p2.3/bm k1 iovdd1 iovdd3 iovdd2 vdd1 dvdd_1v8 dvdd_2v5 dgnd1 dgnd2 iognd1 iognd2 iognd3 10k ? d v dd v dd1 0.47f 0.47f vdd1 10k ? 1 0 k ? v i n v o u t e n / u v l o g n d avdd dvdd agnd dgnd agnd adp7102ardz3.3 v i n s e n s e / a d j p g vdd1 dgnd dgnd1 1 0 f 1 2 p f d g n d n c dvdd agnd agnd1 k 2 e10 b10 e9 b9 c3 interface board connector rx nc nc nc nc avdd_reg1 d10 g11 l6 b6 a6 b1 d11 j1 k6 l2 l1 13754-009 0.1f 0.1f 0.1f 10f 0.1f 10f 0.1f 10f 1.6 ? 1.6 ?
data sheet ADUCM322 rev. 0 | page 23 of 23 packaging and ordering information outline dimensions figure 14. 96-ball chip scale package ball grid array [csp_bga] (bc-96-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option downloader ordering quantity ADUCM322bbcz ?40c to +105c 96-ball csp_bga bc-96-2 mdio 429 ADUCM322bbcz-rl ?40c to +105c 96-ball csp_bga bc-96-2 mdio 2,500 ev-ADUCM322qspz evaluation board with quickstart development system mdio 1 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). 6.10 6.00 sq 5.90 5.00 ref sq 0.35 0.30 0.25 04-02-2013-a coplanarity 0.08 a b c d e f g h j k l 7 63 21 5 4 ball diameter 0.50 bsc 0.50 ref detail a a1 ball corner a1 ball corner detail a bottom view top view seating plane 1.200 1.083 1.000 89 1011 compliant to jedec standards mo-195-ac with the exception to ball count. 0.223 nom 0.173 min 0.93 0.86 0.79 ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13754-0-2/16(0) www.analog.com/ADUCM322

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